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Freescale Semiconductor Technical Data
MM908E624 Internal Rev 4.0, 12/2004
Integrated Triple High-Side Switch with Embedded MCU and LIN Serial Communication for Relay Drivers
The 908E624 is an integrated single-package solution that includes a high-performance HC08 microcontroller with a SMARTMOSTM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), serial peripheral interface (SPI) (only internal), and an internal clock generator module. The analog control die provides three high-side outputs with diagnostic functions, voltage regulator, watchdog, operational amplifier, and local interconnect network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive high-current motors applications using relays (e.g., window lifts, fans, and sun roofs). Features * High-Performance M68HC908EY16 Core * 16 K Bytes of On-Chip Flash Memory * 512 Bytes of RAM * Internal Clock Generator Module * Two 16-Bit, 2-Channel Timers * 10-Bit Analog-to-Digital Converter (ADC) * LIN Physical Layer Interface * Low Dropout Voltage Regulator * Three High-Side Outputs * Two Wake-Up Inputs * 16 Microcontroller I/Os
VBAT VSUP1 LIN Interface +5.0 V LIN VREFH VDDA EVDD VCC VDD VREFL VSSA EVSS AGND GND RxD PTE1/RxD RSTB RSTB_A IRQB IRQB_A PTD0/TACH0 PWMin Microcontroller Ports PTA0-4 PTB1;3-7 PTC2-4 PTD1/TACH1 HS2 +E VSUP2 HS3 L1 L2
908E624
TRIPLE HIGH-SIDE SWITCH WITH EMBEDDED MCU AND LIN
DW SUFFIX 98ASA99294D 54-TERMINAL SOICW
ORDERING INFORMATION
Device MM908E624ACDWB/R Temperature Range (TA) -40C to 85C Package 54 SOICW
HS1
M
To Microcontroller A/D Channel OUT -E WDCONF
Figure 1. 908E624 Simplified Application Diagram
This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2004. All rights reserved.
Internal Bus
PTA1/KBD1 PTA0/KBD0 PTD1/TACH1
PTD1/TACH1
PTB7/AD7/TBCH1 PTD0/TACH0 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTE1/RxD PTB2/AD2 PTB1/AD1 PTE0/TxD PTB0/AD0
PORT A
PTA2/KBD2 PTC0/MISO
DDRA
PORT C
PTC4/OSC1
PTA3/KBD3 PTC1/MOSI
DDRC
DDRD
PORT D
PORT B
DDRB
DDRE
PORT E
2
RST_A IRQ_A PTD0/TACH0 PTE1/RXD IRQ VREFL AGND RXD VSUP1 VSUP2 PWMIN EVDD GND LIN EVSS VSSA WDCONF RST
908E624
M68HC08 CPU
VSUP1
ALU 5-Bit Keyboard Interrupt Module Single Breakpoint Break Module
Internal Block Diagram
VREFH
PTE0/TXD TXD Voltage Regulator LIN Physical Layer
Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes 2-channel Timer Interface Module B 2-channel Timer Interface Module A
VDDA
CPU Registers
PTA0/KBD0
VDD
PTA1/KBD1 Window Watchdog PWMIN
PTA2/KBD2
FLASH programming (burn in) ROM, 1024 Bytes
VSUP2
User Flash Vector Space, 36 Bytes Enhanced Serial Communication Interface Module Computer Operating Properly Module
PTA3/KBD3
Internal Clock Generator Module
High Side Driver & Diagnostic VSUP2 PWMIN
HS1
OSC2
OSC1
PTA4/KBD4 Reset Control Module
PTB1/AD1
24 Internal System Integration Module Serial Pheripheral Interface Module
RST
High Side Driver & Diagnostic
HS2
PTB3/AD3
Single External IRQ Module Configuration Register Module
IRQ
VSUP2
PTB4/AD4
10 Bit Analog-to-Digital Converter Module Periodic Wakeup Timebase Module
VREFH
VDDA
VREFL
High Side Driver & Diagnostic PTA6/SS SS
HS3
PTB5/AD5
VSSA
PTB6/AD6/TBCH0
POWER Arbiter Module
VDD
VSS
PTC0/MISO
MISO Wake Up Input 1 MOSI L1
PTB7/AD7/TBCH1
Power-On Reset Module Prescaler Module
PTC1/MOSI
SPI & Mode Control
PTC2/MCLK
Security Module BEMF Module
INTERNAL BLOCK DIAGRAM
L2 SPSCK
PTA5/SPSCK
PTA6/SS PTA5/SPSCK PTA4/KBD4 PTC2/MCLK PTC3/OSC2 PTC4/OSC1
Wake Up Input 2
PTC3/OSC2
VCC
+E
Amplifier
-E
FLSVPP
OUT
MCU Die
Analog Die
Analog Integrated Circuit Device Data Freescale Semiconductor
Figure 2. 908E624 Simplified Internal Block
Terminal Connections
TERMINAL CONNECTIONS
PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0 PTD1/TACH1 NC NC NC PWMIN RST_A IRQ_A NC NC NC L1 L2 HS3 HS2 HS1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD NC RXD WDCONF +E -E OUT VCC AGND VDD NC VSUP1 GND LIN VSUP2
Figure 3. Terminal Connections Table 1. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 17.
Die MCU Terminal 1 2 6 7 8 11 3 4 5 9 10 12 13 14, 15, 16, 20, 21, 22, 32, 41 42 Terminal Name PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK
IRQ RST
Formal Name Port B I/Os
Definition These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU.
MCU
Port C I/Os
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. This terminal is an asynchronous external interrupt input terminal. This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. Not connected.
MCU MCU MCU --
External Interrupt Input External Reset Port D I/Os No Connect
PTD0/TACH0 PTD1/TACH1 NC
MCU
PTE1/RXD
Port E I/O
This terminal is a special-function, bidirectional I/O port terminal that can is shared with other functional modules in the MCU.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Terminal Connections
Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 17.
Die MCU MCU MCU MCU Terminal 43 48 44 47 45 46 49 50 52 53 54 51 17 18 19 23 24 25 26 27 31 28 29 30 34 33 35 36 37 38 39 Terminal Name VREFL VREFH VSSA VDDA EVSS EVDD PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 FLSVPP PWMIN
RST_A IRQ_A L1 L2
Formal Name ADC References ADC Supply Terminals MCU Power Supply Terminals Port A I/Os
Definition These terminals are the reference voltage terminals for the analog-todigital converter (ADC). These terminals are the power supply terminals for the analog-to-digital converter. These terminals are the ground and power supply terminals, respectively. The MCU operates from a single-power supply. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU.
MCU Analog Analog Analog Analog Analog
Test Terminal Direct High-Side Control Input Internal Reset Output Internal Interrupt Output Wake-Up Inputs High-Side Output
For test purposes only. Do not connect in the application. This terminal allows the enabling and PWM control of the high-side HS1 and HS2 terminals. This terminal is the reset output terminal of the analog die. This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. These terminals are the wake-up inputs of the analog chip. These output terminals are low RDS(ON) high-side switches.
HS3 HS2 HS1 VSUP1 VSUP2 LIN GND AGND VDD VCC OUT -E +E WDCONF
Analog Analog Analog Analog Analog Analog Analog Analog
Power Supply Terminals LIN Bus Power Ground Terminals Voltage Regulator Output Amplifier Power Supply Amplifier Output Amplifier Inputs Watchdog Configuration Terminal LIN Transceiver Output
These terminals are device power supply terminals. This terminal represents the single-wire bus transmitter and receiver. These terminals are device power ground connections. The +5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller. This terminal is the single +5.0 V power supply for the operational amplifier. This terminal is the output of the operational amplifier. These terminals are the amplifier inverted and non-inverted inputs. This input terminal is for configuration of the watchdog period and allows the disabling of the watchdog. This terminal is the output of LIN transceiver.
Analog
40
RXD
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Analog Integrated Circuit Device Data Freescale Semiconductor
Maximum Ratings
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device.
Rating Electrical Ratings Supply Voltage Analog Chip Supply Voltage under Normal Operation (Steady-State) Analog Chip Supply Voltage under Transient Conditions MCU Chip Supply Voltage Input Terminal Voltage Analog Chip Microcontroller Chip Maximum Microcontroller Current per Terminal All Terminals except VDD, VSS, PTA0:PTA6, PTC0:PTC1 PTA0:PTA6, PTC0:PTC1 Terminals Maximum Microcontroller VSS Output Current Maximum Microcontroller VDD Input Current Current Sense Amplifier Maximum Input Voltage, +E, -E Terminals Maximum Input Current, +E, -E Terminals Maximum Output Voltage, OUT Terminal Maximum Output Current, OUT Terminal LIN Supply Voltage Normal Operation (Steady-State) Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 15) L1 and L2 Terminal Voltage Normal Operation with a 33 k resistor (Steady-State) Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 15) ESD Voltage Human Body Model (1) Machine Model (2) Charge Device Model (3) VESD1 VESD2 VESD3 2000 100 500 VWAKE(SS) VWAKE(PK) -18 to 40 -100 to 100 V VBUS(SS) VBUS(PK) -18 to 40 -150 to 100 V V +E-E I +E-E VOUT IOUT -0.3 to 7.0 20 -0.3 to VCC +0.3 20 V mA V mA V IPIN(1) IPIN(2) IMVSS IMVDD 15 25 100 100 mA mA VIN(ANALOG) VIN(MCU) -0.3 to VDD +0.3 VSS -0.3 to VDD +0.3 mA VSUP(SS) VSUP(PK) VDD -0.3 to 27 -0.3 to 40 -0.3 to 5.5 V V Symbol Value Unit
Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 2. 3. ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP = 0 ). ESD3 testing is performed in accordance with Charge Device Model, Robotic (CZAP = 4.0 pF).
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Analog Integrated Circuit Device Data Freescale Semiconductor
5
Maximum Ratings
Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device.
Rating Thermal Ratings Operating Ambient Temperature Operating Junction Temperature (4) Analog MCU Storage Temperature Peak Package Reflow Temperature During Solder Mounting (5) Thermal Resistance, Junction to Ambient (6) , (7) TJ(ANALOG) TJ(MCU) TSTG TSOLDER RJA -40 to 150 -40 to 125 -40 to 150 245 36 C C C C C/ W TA -40 to 85 C Symbol Value Unit
Notes 4. Die temperature of analog and MCU is linked via the package. High temperature on analog die can lead to a high MCU temperature. 5. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 6. All power outputs ON and dissipating equal power. 7. Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Static Electrical Characteristics
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Supply Voltage Range Nominal Operating Voltage Functional Operating Voltage (8) Supply Current Range Normal Mode (9) VSUP = 13.5 V, Analog Chip in Normal Mode, MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled Stop Mode (9), (10) VSUP = 13.5 V Sleep Mode (9), (10) VSUP = 13.5 V Digital Interface Ratings (Analog Die) Output Terminal RST_A Low-State Output Voltage (IOUT = -1.5 mA) High-State Output Current (VOUT > 3.5 V) Pulldown Current Limitation Output Terminal IRQ_A Low-State Output Voltage (IOUT = -1.5 mA) High-State Output Voltage (IOUT = 250 A) Output Terminal RXD Low-State Output Voltage (IOUT = -1.5 mA) High-State Output Voltage (IOUT = 250 A) Capacitance
(11)
Symbol
Min
Typ
Max
Unit
VSUP VSUPOP
5.5 --
-- --
18 27
V V
IRUN -- ISTOP ISLEEP -- -- 60 35 75 45 20 --
mA
A A
VOL IOH IOL_MAX
-- -- -1.5
-- 250 --
0.4 -- -8.0
V A mA V
VOL VOH
-- 3.85
-- --
0.4 --
VOL VOH CIN
-- 3.85 --
-- -- 4.0
0.4 -- --
V V pF
Input Terminal PWMIN Input Logic Low Voltage Input Logic High Voltage Input Current Capacitance (11) Terminal TXD, SS-Pullup Current VIL VIH IIN CIN IPULLUP -- 3.5 -10 -- -- -- -- -- 4.0 40 1.5 -- 10 -- -- V V A pF A
Notes 8. Device is fully functional. All functions are operating. Overtemperature may occur. 9. Total current (IVSUP1 + IVSUP2) measured at GND terminal. 10. 11. Stop and Sleep mode current will increase if VSUP exceeds 15 V. This parameter is guaranteed by process monitoring but is not production tested.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Static Electrical Characteristics
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic System Resets and Interrupts Low-Voltage Reset (LVR) Threshold Low-Voltage Interrupt (LVI) Threshold Hysteresis High-Voltage Interrupt (HVI) Threshold Hysteresis Voltage Regulator
(12)
Symbol
Min
Typ
Max
Unit
V V LVRON 3.6 4.0 4.4 V V LVI V LVI_HYS 5.7 -- 6.0 1.0 6.6 --
V HVI V HVI_HYS
18 --
19.25 220
20.5 --
V mV
Normal Mode Output Voltage 2.0 mA < IDD < 50 mA, 5.5 V < VSUP < 27 V Normal Mode Output Current Limitation (13) Dropout Voltage (14) IDD = 50 mA Stop Mode Output Voltage (15) Stop Mode Regulator Current Limitation Line Regulation Normal Mode, 5.5 V < VSUP < 27 V, IDD = 10 mA Stop Mode, 5.5 V < VSUP < 27 V, IDD = 2.0 mA Load Regulation Normal Mode, 1.0 mA < IDD < 50 mA, VSUP = 18 V Stop Mode, 1.0 mA < IDD < 5 mA, VSUP = 18 V Overtemperature Pre-Warning (Junction) (16) Thermal Shutdown Temperature (Junction) (16) Temperature Threshold Difference TSD -TPRE Notes 12. 13. 14. 15. 16.
V DDRUN 4.75 IDDRUN V DDDROP -- V DDSTOP IDDSTOP 4.75 4.0 0.1 5.0 8.0 0.2 5.25 14 50 5.0 110 5.25 200
V
mA V
V mA mV
LR RUN LR STOP
-- --
20 10
150 100 mV
LD RUN LD STOP T PRE T SD TSD-TPRE
-- -- 120 155
40 40 135 170
150 150 160 C C C
20
30
45
Specification with external capacitor 1.0 F< C < 10 F and 200 m ESR 1.0 . Capacitor value up to 47 F can be used. Total VDD regulator current. A 5.0 mA current for operational amplifier is included. Digital output supplied from VDD. Measured when voltage has dropped 100 mV below its nominal value. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage specification. This parameter is guaranteed by process monitoring but not production tested
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Analog Integrated Circuit Device Data Freescale Semiconductor
Static Electrical Characteristics
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Window Watchdog Configuration Terminal (WDCONF) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy) (17) LIN Physical Layer LIN Transceiver Output Level Recessive State, TXD HIGH, IOUT = 1.0 A Dominant State, TXD LOW, 500 External Pullup Resistor Normal Mode Pullup Resistor to VSUP Stop, Sleep Mode Pullup Current Source Output Current Shutdown Threshold Output Current Shutdown Delay Leakage Current to GND VSUP Disconnected, VBUS at 18 V Recessive State, VSUP 8.0 V to 18 V, VBUS 8.0 V to 18 V, VBUS VSUP GND Disconnected, VGND = VSUP, VBUS at -18 V LIN Receiver Receiver Threshold Dominant Receiver Threshold Recessive Receiver Threshold Center Receiver Threshold Hysteresis V BUS_DOM V BUS_REC V BUS_CNT V BUS_HYS -- 0.6 0.475 -- -- -- 0.5 -- 0.4 -- 0.525 0.175 V LIN_REC V LIN_DOM R PU IPU IOV-CUR IOV-DELAY IBUS -- 0 -1.0 1.0 3.0 -- 10 20 1.0 VSUP VSUP -1 -- 20 -- 50 -- -- -- 30 2.0 75 10 -- 1.4 60 -- 150 -- k A mA s A V REXT WDCACC 10 -15 -- -- 100 15 k % Symbol Min Typ Max Unit
Notes 17. Watchdog timing period calculation formula: PWD = 0.991 * REXT +0.648 (REXT in k and PWD in ms).
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Static Electrical Characteristics
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic High-Side Outputs HS1 and HS2 Switch On Resistance TJ = 25C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 125C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 125C, ILOAD = 120 mA, 5.5 V < VSUP > 9.0 V Output Current Limit Overtemperature Shutdown Leakage Current High-Side Output HS3 Switch On Resistance TJ = 25C, ILOAD = 50 m A, VSUP > 9.0 V TJ = 125C, ILOAD = 50 mA, VSUP > 9.0 V TJ = 125C, ILOAD = 30 mA, 5.5 V < VSUP > 9.0 V Output Current Limitation Overtemperature Shutdown (18), (19) Leakage Current Output Clamp Voltage IOUT = -100 mA Notes 18. This parameter is guaranteed by process monitoring but it is not production tested 19. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI. ILIM THSSD ILEAK VCL -6.0 -- -- RDS(ON) -- -- -- 60 155 -- -- -- -- 100 -- -- 7.0 10 14 200 190 10
(18), (19)
Symbol
Min
Typ
Max
Unit
RDS(ON) -- -- -- ILIM THSSD ILEAK 300 155 -- 2.0 -- 3.0 -- -- -- 2.5 4.5 -- 600 190 10
mA
C
A
mA C
A V
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Analog Integrated Circuit Device Data Freescale Semiconductor
Static Electrical Characteristics
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Sense Current Amplifier Rail to Rail Input Voltage Output Voltage Range Output Current 1.0 mA Output Current 5.0 mA Input Bias Current Input Offset Current Input Offset Voltage Supply Voltage Rejection Ratio (20) Common Mode Rejection Ratio Gain Bandwidth (20) Slew Rate Phase Margin (for Gain = 1, Load 100 pF/ /5.0 k (20) Open Loop Gain L1 and L2 Inputs Negative Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V Positive Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V Hysteresis 5.5 V < VSUP < 27 V Input Current -0.2 V < VIN < 40 V Notes 20. This parameter is guaranteed by process monitoring but is not production tested. IIN -10 -- 10 VHYST 0.5 -- 1.3 A VTHP 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.5 4.7 V VTHN 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.5 3.7 V V
(20)
Symbol
Min
Typ
Max
Unit
VIMC
-0.1
--
VCC +0.1
V V
VOUT1 VOUT2 IB IO VIO SVR CMR GBP SR PHMO OLG
0.1 0.3 -- -100 -25 60 70 1.0 0.5 40 --
-- -- -- -- -- -- -- -- -- -- 85
VCC -0.1 VCC -0.3 250 100 25 -- -- -- -- -- -- nA nA mV dB dB MHz V/s dB
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Dynamic Electrical Characteristics
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic LIN Physical Layer Driver Characteristics for Normal Slew Rate (21), (22) Dominant Propagation Delay TXD to LIN Dominant Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Propagation Delay Symmetry: t DOM-MIN - t REC-MAX Propagation Delay Symmetry: t DOM-MAX - t REC-MIN Driver Characteristics for Slow Slew Rate (21), (23) Dominant Propagation Delay TXD to LIN Dominant Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Propagation Delay Symmetry: t DOM-MIN - t REC-MAX Propagation Delay Symmetry: t DOM-MAX - t REC-MIN Driver Characteristics for Fast Slew Rate LIN High Slew Rate (Programming Mode) Receiver Characteristics and Wake-Up Timings Receiver Dominant Propagation Delay (24) Receiver Recessive Propagation Delay (24) Receiver Propagation Delay Symmetry Bus Wake-Up Deglitcher Bus Wake-Up Event Reported
(25)
Symbol
Min
Typ
Max
Unit
t DOM-MIN t DOM-MAX t REC-MIN t REC-MAX dt1 dt2
-- -- -- -- -10.44 --
-- -- -- -- -- --
50 50 50 50 -- 11
s s s s s s
t DOM-MIN t DOM-MAX t REC-MIN t REC-MAX dt1s dt2s
-- -- -- -- -22 --
-- -- -- -- -- --
100 100 100 100 -- 23
s s s s s s
SRFAST
--
15
--
V/s
t RL t RH t R-SYM t PROPWL t WAKE
-- -- -2.0 35 --
3.5 3.5 --
6.0 6.0 2.0 80
s s s s s
20
--
Notes 21. VSUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 k, 6.8 nF/660 , 10 nF/500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. 22. See Figure 6, page 15. 23. See Figure 7, page 16. 24. Measured between LIN signal threshold VIL or VIH and 50% of RXD signal. 25. t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 16. In Sleep mode the VDD rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Dynamic Electrical Characteristics
Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SPI Interface Timing SPI Operating Recommended Frequency L1 AND L2 INPUTS Wake-Up Filter Time (26) Window Watchdog Configuration Terminal (WDCONF) Watchdog Period External Resistor REXT = 10 k (1%) External Resistor REXT = 100 k (1%) Without External Resistor REXT (WDCONF Terminal Open) State Machine Timing Reset Low-Level Duration after VDD High Interrupt Low-Level Duration Normal Request Mode Timeout Delay Between SPI Command and HS1/HS2/HS3 Turn On
(27) , (28)
Symbol
Min
Typ
Max
Unit
f SPIOP
0.25
--
4.0
MHz
t WUF
8.0
20
38
s
PWD -- -- 97 10.558 99.748 150 -- -- 205
ms
t RST t INT NR TOUT t S-HSON t S-HSOFF t S-NR2N t W-SSB
0.65 7.0 97 -- -- 6.0
1.0 10 150 3.0 3.0 35
1.35 13 205 10 10 70
ms s ms s s s s
Delay Between SPI Command and HS1/HS2/HS3 Turn Off (27)
, (28)
Delay Between Normal Request and Normal Mode After W/D Trigger Command (29) Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode (VDD On and Reset High) Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI Command Delay Between Interrupt Pulse and First SPI Command Accepted Minimum Time Between Two Rising Edges on SS Notes 26. 27. 28. 29.
15 t W-SPI 90 t S-1STSPI t 2SSB 30 15
40
80 s
-- -- --
N/A N/A -- s s
This parameter is guaranteed by process monitoring but is not production tested. Delay between turn-on or turn-off command and high-side on or high-side off, excluding rise or fall time due to external load. Delay between the end of the SPI command (rising edge of the SS) and start of device activation/deactivation. This parameter is guaranteed by process monitoring but it is not production tested.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Microcontroller Parametrics
MICROCONTROLLER PARAMETRICS
Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
Module Core Timer Flash RAM ADC SPI ESCI Description High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Two 16-Bit Timers with 2 Channels (TIM A and TIM B) 16 K Bytes 512 Bytes 10-Bit Analog-to-Digital Converter SPI Module Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment Internal Clock Generation Module
ICG
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Analog Integrated Circuit Device Data Freescale Semiconductor
Timing Diagrams
TIMING DIAGRAMS
LIN, L1, and L2
Transient Pulse Generator
10 k 10k
1.0 nF 1nF
Note Waveform in accordance with ISO7637 Part 1, Test Pulses 1, 2, 3a, and 3b.
Figure 4. Test Circuit for Transient Test Pulses
VSUP
TXD LIN RXD
R0
R0 R0 and C0 combinations: and C0 Combinations: * 1.0 1k Ohm and nF - k and 1.0 1nF * 600660and 6.8 nF - Ohm and 6.8nF * 500500and 10 nF10nF - Ohm and
C0
Figure 5. Test Circuit for LIN Timing Measurements
TXD
VLIN_REC Vrec
t REC-MAX Trec-max
Tdom-min t DOM-MIN 58.1% Vsup 58.1% VSUP 40% Vsup 40% VSUP 28.4% Vsup 28.4% VSUP 74.4% V 74.4% Vsup SUP 60% VSUP 60% Vsup 42.2% VSUP 42.4%Vsup
LIN
tTdom-max DOM-MAX
t REC-MIN
RXD
Trec-min
t RL
TrL
t RH
TrH
Figure 6. LIN Timing Measurements for Normal Slew Rate
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Timing Diagrams
TXD
VLIN_REC Vrec
t REC-MAX Trec-max
Tdom-min t DOM-MIN 58.1% Vsup 61.6% VSUP 40% Vsup 40% VSUP 28.4% Vsup 25.1% VSUP 74.4% V 77.8% Vsup SUP 60% VSUP 60% Vsup 42.2% VSUP 38.9%Vsup
LIN
tTdom-max DOM-MAX
t REC-MIN
RXD
Trec-min
t RL
TrL
t RH
TrH
Figure 7. LIN Timing Measurements for Slow Slew Rate
Vrec VLIN_REC
LIN
0.4VSUP 0.4 V
SUP
Dominantlevel Dominant Level
VDD
tTpropWL PROPWL
tTwake WAKE
Figure 8. Wake-Up Sleep Mode Timing
VLIN_REC Vrec
LIN
0.4VSUP 0.4 VSUP
Dominant level Dominant Level
IRQ_A
tTpropWL PROPWL
tTwake WAKE
Figure 9. Wake-Up Stop Mode Timing
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Analog Integrated Circuit Device Data Freescale Semiconductor
Functional Description Introduction
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 908E624 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E624 is well suited to perform relay control in applications like window lift, sunroof, etc., via a three-wire LIN bus. The device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip. Power switches are provided on the SmartMOS IC configured as high-side outputs. Other ports are also provided, which include an operational amplifier port and two wake-up terminals. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and one for ground.
FUNCTIONAL TERMINAL DESCRIPTION
See Figure 1, 908E624 Simplified Application Diagram, page 1, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package.
PORT D I/O TERMINALS
PTD1/TACH1 and PTD0/TACH0/BEMF are specialfunction, bidirectional I/O port terminals that can also be programmed to be timer terminals. For details refer to the 68HC908EY16 datasheet.
PORT A I/O TERMINALS
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt terminals KBD0:KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/SS terminal is likewise not accessible. For details refer to the 68HC908EY16 datasheet.
PORT E I/O TERMINAL
PTE1/RXD and PTE0/TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. For details refer to the 68HC908EY16 datasheet.
PORT B I/O TERMINALS
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6:PTB7 terminals are also shared with the Timer B module. The PTB0/AD0 and PTB2/AD2 terminals are not accessible in this device. For details refer to the 68HC908EY16 datasheet.
EXTERNAL INTERRUPT TERMINAL (IRQ)
The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet.
EXTERNAL RESET TERMINAL (RST)
A logic [0] on the RST terminal forces the MCU to a known startup state. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. Important To ensure proper operation, do not add any external pullup resistor. For details refer to the 68HC908EY16 datasheet.
PORT C I/O TERMINALS
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet.
MCU POWER SUPPLY TERMINALS (EVDD AND EVSS)
EVDD and EVSS are the power supply and ground terminals, respectively. The MCU operates from a singlepower supply.
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Functional Description Functional Terminal Description
Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet.
INTERRUPT TERMINAL (IRQ_A)
IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal must be connected to the IRQ terminal of the MCU.
ADC SUPPLY TERMINALS (VDDA AND VSSA)
VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet.
WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF)
This terminal is the configuration terminal for the internal watchdog. A resistor is connected to this terminal. The resistor value defines the watchdog period. If the terminal is open, the watchdog period is fixed to its default value. The watchdog can be disabled (e.g., for flash programming or software debugging) by connecting this terminal to GND.
ADC REFERENCE TERMINALS (VREFL AND VREFH)
VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSSA via separate traces. For details refer to the 68HC908EY16 datasheet.
POWER SUPPLY TERMINALS (VSUP1 AND VSUP2)
This VSUP1 power supply terminal supplies the voltage regulator, the internal logic, and LIN transceiver. This VSUP2 power supply terminal is the positive supply for the high-side switches.
POWER GROUND TERMINAL (GND)
This terminal is the device ground connection.
HIGH-SIDE OUTPUT TERMINALS (HS1 AND HS2)
These terminals are high-side switch outputs to drive loads such as relays or lamps. Each switch is protected with overtemperature and current limit (overcurrent). The output has an internal clamp circuitry for inductive load. The HS1 and HS2 outputs are controlled by SPI and have a direct enabled input (PWMIN) for PWM capability.
TEST TERMINAL (FLSVPP)
This terminal is for test purposes only. Do not connect in the application.
PWMIN TERMINAL
This terminal is the direct PWM input for high-side outputs 1 and 2 (HS1 and HS2). If no PWM control is required, PWMIN must be connected to VDD to enable the HS1 and HS2 outputs.
HIGH-SIDE OUTPUT TERMINAL (HS3)
This high-side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. The switch is protected with overtemperature and current limit (overcurrent). The output is controlled only by SPI.
LIN TRANSCEIVER OUTPUT TERMINAL (RXD)
This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller's Enhanced Serial Communications Interface (ESCI) module (RXD terminal).
LIN BUS TERMINAL (LIN)
The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification.
RESET TERMINAL (RST_A)
RST_A is the reset output terminal of the analog die and must be connected to the RST terminal of the MCU.
WAKE-UP TERMINALS (L1 AND L2)
These terminals are high-voltage capable inputs used to sense external switches and to wake up the device from Sleep or Stop mode. During Normal mode the state of these terminals can be read through SPI.
Important To ensure proper operation, do not add any external pullup resistor.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Functional Description Functional Terminal Description
SENSE AMPLIFIER TERMINALS (E+, E-, OUT, VCC)
These are the terminals of the single-supply sense amplifier. * The E+ and E- input terminals are the non-inverting and inverting inputs of the amplifier, respectively. * The OUT terminal is the output terminal of the current sense amplifier. * The VCC terminal is the +5.0 V single-supply connection.
intended to supply the embedded microcontroller. The terminal is protected against shorts to GND with an integrated current limit (temperature shutdown could occur). Important The VDD, EVDD, VDDA, and VREFH terminals must be connected together.
VOLTAGE REGULATOR AND SENSE AMPLIFIER GROUND TERMINAL (AGND)
The AGND terminal is the ground terminal of the voltage regulator and the Sense Amplifier. Important GND, AGND, VSS, EVSS, VSSA, and VREFL terminals must be connected together.
+5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD)
The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is
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Functional Description Functional Device Operation
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES 908E624 ANALOG DIE MODES OF OPERATION
The 908E624 offers three operating modes: Normal (Run), Stop, and Sleep. In Normal mode the device is active and is operating under normal application conditions. The Stop and Sleep modes are low-power modes with wake-up capabilities. In Stop mode the voltage regulator still supplies the MCU with VDD (limited current capability) and in Sleep mode the voltage regulator is turned off (VDD = 0 V). Wake-up from Stop mode is initiated by a wake-up interrupt. Wakeup from Sleep mode is done by a reset and the voltage regulator is turned back on. The selection of the different modes is controlled by the MODE1:2 bits in the SPI Control register. Figure 10 describes how transitions are done between the different operating modes and Table 6, page 21, gives an overview of the operating mode.
Normal Request Timeout Expired(NRTOUT) ) Normal Request timeout expired (NRTOUT VDD Low VDD Low VDD High and
Power Down
Power Up
Reset
Reset Delay (t RST) Expired VDD High and Reset Delay (tRST) expired
Normal Request
WDdisabled WD Disabled WD Trigger WD trigger
VDDLow Low V
DD
WD Failed WD failed VDDLow (>NRTOUT) expired) Expired VDD LOW (>NR TOUT and and LVF = 0 VSUV = 0
Normal
Sleep Command STOP Command
Sleep Command SLEEP Command
Wake-Up (Reset) Wake-Up (Reset)
Sleep
Stop
VDD Low VDD Low
Legend WD: Watchdog Notes: WD Disabled: Watchdog disabled (WDCONF terminal connected to GND) WD - means Watchdog WD Trigger: Watchdog is triggered by SPI command WD Failed:WD disabled - trigger or trigger occurs in closed window No watchdog means Watchdog disabled (WDCONF terminal connected to GND) WD trigger - means Watchdog is triggered by SPI command Stop Command: Stop command sent via SPI WD failed - means no Watchdog trigger or trigger occurs in closed window Sleep Command: Sleep command sent via SPI STOP Command - means STOP command sent via SPI Wake-Up: L1 or L2 state change or LIN bus wake-up or SS rising edge SLEEP Command - means SLEEP command send via SPI Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge
Figure 10. Operating Modes and Transitions
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Analog Integrated Circuit Device Data Freescale Semiconductor
Wake-Up Interrupt Wake-Up Interrupt
Functional Description Functional Device Operation
Table 6. Operating Modes Overview
Device Mode Reset Normal Request Normal (Run) Stop Voltage Regulator VDD ON VDD ON VDD ON VDD ON with limited current capability VDD OFF Wake-Up Capabilities N/A N/A N/A LIN wake-up, L1, L2 state change, SS rising edge LIN wake-up L1, L2 state change
RST_A
Output LOW HIGH HIGH
Watchdog Function Disabled 150 ms time out if WD enabled Window WD if enabled Disabled
HS1, HS2, and HS3 Disabled Enabled Enabled
LIN Interface Recessive only Transmit and receive Transmit and receive Recessive state with wake-up capability Recessive state with wake-up capability
Sense Amplifier Not active Not active Active
HIGH
Disabled
Not active
Sleep
LOW
Disabled
Disabled
Not active
INTERRUPTS
In Normal (Run) mode the 908E624 has four different interrupt sources. An interrupt pulse on the IRQ_A terminal is generated to report a fault to the MCU. All interrupts are not maskable and cannot be disabled. After an Interrupt the INTSRC bit in the SPI Status register is set, indicating the source of the event. This interrupt source information is only transferred once, and the INTSRC bit is cleared automatically.
Low-Voltage Interrupt
After a wake-up interrupt, the INTSRC bit in the Serial Peripheral Interface (SPI) Status register is set, indicating the source of the event. This wake-up source information is only transferred once, and the INTSRC bit is cleared automatically. Figure 11, page 22, describes the Stop/Wake-Up procedure.
VOLTAGE REGULATOR TEMPERATURE PREWARNING (VDDT)
Voltage regulator temperature prewarning (VDDT) is generated if the voltage regulator temperature is above the TPRE threshold, it will set the VDDT bit in the SPI Status register and an interrupt will be initiated. The VDDT bit remains set as long as the error condition is present. During Sleep and Stop mode the voltage regulator temperature prewarning circuitry is disabled.
Low-voltage interrupt (LVI) is related to external supply voltage VSUP1. If this voltage falls below the LVI threshold, it will set the LVF bit in the SPI Status register and an interrupt will be initiated. The LVF bit remains set as long as the Lowvoltage condition is present. During Sleep and Stop mode the low-voltage interrupt circuitry is disabled.
High-Voltage Interrupt
HIGH-SIDE SWITCH THERMAL SHUTDOWN (HSST)
The high-side switch thermal shutdown HSST is generated if one of the high-side switches HS1:HS3 is above the HSST threshold, it will shutdown the corresponding Highside switch, set the HSST flag in the SPI Status register and an interrupt will be initiated. The HSST bit remains set as long as the error condition is present. During Sleep and Stop mode the high-side switch thermal shutdown circuitry is disabled.
High-voltage interrupt (HVI) is related to external supply voltage VSUP1. If this voltage rises above the HVI threshold, it will set the HVF bit in the SPI Status register and an interrupt will be initiated. The HVF bit remains set as long as the high-voltage condition is present. During Sleep and Stop mode the low-voltage interrupt circuitry is disabled.
Wake-Up Interrupts
In Stop mode the IRQ_A terminal reports wake-up events on the L1, L2, or the LIN bus to the MCU. All wake-up interrupts are not maskable and cannot be disabled.
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Functional Description Functional Device Operation
ANALOG DIE INPUTS/OUTPUTS
MCU
From Reset
Power Die
High-Side Output Terminals HS1 and HS2
initialize
operate
These are two high-side switches used to drive loads such as relays or lamps. They are protected with overtemperature and current limit (overcurrent) and include an active internal clamp circuitry for inductive load drive. Control is done using the SPI Control register. PWM capability is offered through the PWMIN input terminal. The high-side switch is turned on if both the HSxON bit in the SPI Control register is set and the PWMIN input is HIGH (refer to Figure 12, page 23). In order to have HS1 on, the PWMIN must be HIGH and bit HS1ON must be set. The same applies to the HS2 output. If no PWM control is required, PWMIN must be connected to the VDD terminal.
Switch to VREG low current mode
SPI: 2x STOP Command
Current Limit (Overcurrent) Protection
These high-side switches feature current limit to protect them against overcurrent and short circuit conditions.
Overtemperature Protection
Wake Up on LIN or L1, L2?
STOP
IRQ interrupt ?
Assert IRQ
If an overtemperature condition occurs on any of the three high-side switches, the faulty switch is turned off and latched off until the HS1 (or HS2 or HS3) bit is set to "1" in the SPI Control register. The failure is reported by the HSST bit in the SPI Control register.
Sleep and Stop Mode
In Sleep and Stop modes the high-sides are disabled.
SPI: reason for interrupt Switch to VREG high current mode
High-Side Output HS3
operate
This high-side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. Control is done using the SPI Control register. No direct PWM control is possible on this terminal (refer to Figure 13, page 23).
Current Limit (Overcurrent) Protection
Figure 11. Stop Mode/Wake-Up Procedure
This high-side feature switch feature current limit to protect it against overcurrent and short circuit conditions.
Overtemperature Protection
If an overtemperature condition occurs on any of the three high-side switches, the faulty switch is turned off and latched off until the HS3 (or HS1 or HS2) bit is set to "1" in the SPI Control register. The failure is reported by the HSST bit in the SPI Control register.
Sleep and Stop Mode
In Sleep and Stop mode the high-side is disabled.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Functional Description Functional Device Operation
.
PWMIN
VSUP2
MODE1:2
On/Off HSxON
High-Side Driver
Charge Pump, Current Limit Protection, Overtemperature Protection HSx
Control
Status
Figure 12. High-Side HS1 and HS2 Circuitry
.
MODE1:2
VSUP2
On/Off HS3ON
High-Side Driver
Charge Pump, Current Limit Protection, Overtemperature Protection HS3
Control
Status
Figure 13. High-Side HS3 Circuitry
WINDOW WATCHDOG
The window watchdog is configurable using an external resistor at the WDCONF terminal. The watchdog is cleared through by the MODE1:2 bits in the SPI Control register (refer to Table 8, page 26). A watchdog clear is only allowed in the open window. If the watchdog is cleared in the closed window or has not been cleared at the end of the open window, the watchdog will generate a reset on the RST_A terminal and reset the whole device. Note The watchdog clear in Normal request mode (150 ms) (first watchdog clear) has no window.
Window closed no watchdog clear allowed Window open for watchdog clear
WD timing x 50%
WD timing x 50%
WD period (PWD) WD timing selected by resistor on WDCONF terminal.
Figure 14. Window Watchdog Operation
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Functional Description Functional Device Operation
Watchdog Configuration
Stop Mode
If the WDCONF terminal is left open, the default watchdog period is selected (typ. 150 ms). If no watchdog function is required, the WDCONF terminal must be connected to GND. The watchdog period is calculated using the following formula: PWD [ms] = 0.991 * REXT [k] + 0.648
During Stop mode the Stop mode regulator supplies a regulated output voltage. The Stop mode regulator has a limited output current capability.
Sleep Mode
In Sleep mode the voltage regulator external VDD is turned off.
VOLTAGE REGULATOR
The 908E624 chip contains a low-power, low dropout voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller.
Current Limit (Overcurrent) Protection
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E624, various parameters (e.g., ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the "empty" (0xFF) state: * 0xFD80:0xFDDF Trim and Calibration Values * 0xFFFE:0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used.
The voltage regulator has current limit to protect the device against overcurrent and short circuit conditions.
Overtemperature Protection
OPERATING MODES OF THE MCU
For a detailed description of the operating modes of the MCU, refer to the MC68HC908EY16 datasheet.
The voltage regulator also features an overtemperature protection having an overtemperature warning (Interrupt VDDT) and an overtemperature shutdown.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Functional Description Functional Device Operation
LOGIC COMMANDS AND REGISTERS 908E624 SPI INTERFACE AND CONFIGURATION
The serial peripheral interface creates the communication link between the microcontroller and the analog die of the 908E624. The interface consists of four terminals (see Figure 15): * SS--Slave Select * MOSI--Master-Out Slave-In * MISO--Master-In Slave-Out * SPSCK--Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 8 bits of control information and the slave replies with 8 bits of status data.
SS
Register write data
MOSI
D7
D6
D5
D4
D3
D2
D1
D0
Register read data
MISO
D7
D6
D5
D4
D3
D2
D1
D0
SPSCK
Read data latch
Write data latch
Rising edge of SPSCK Change MISO/MOSI Output
Falling edge of SPSCK Sample MISO/MOSI Input
Figure 15. SPI Protocol
During the inactive phase of the SS (High), the new data transfer is prepared. The falling edge of the SS indicates the start of a new data transfer and puts the MISO in the low-impedance state and latches the analog status data (Register read data). With the rising edge of the SPI clock, SPSCK the data is moved to MISO/MOSI terminals. With the falling edge of the SPI clock SPSCK the data is sampled by the Receiver.
The data transfer is only valid if exactly 8 sample clock edges are present in the active (low) phase of SS. The rising edge of the slave select SS indicates the end of the transfer and latches the write data (MOSI) into the register The SS high forces MISO to the high impedance state.
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Functional Description Functional Device Operation
SPI REGISTER OVERVIEW
Table 7 summarizes the SPI Register bit meaning, reset value, and bit reset condition.
.
Table 7. SPI Register Overview
Read/Write Information Write Read Write Reset Value Write Reset Condition Bit D7 LINSL2 INTSRC (30) 0 POR, RESET D6 LINSL1 LINWU or LINFAIL 0 POR, RESET D5 LIN-PU HVF 0 POR D4 HS3ON LVF or BATFAIL (31) 0 POR, RESET D3 HS2ON VDDT 0 POR, RESET D2 HS1ON HSST 0 POR, RESET D1 MODE2 L2 -- -- D0 MODE1 L1 -- --
Notes 30. D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source. 31. The first SPI read after reset returns the BATFAIL flag state on bit D4.
SPI Control Register (Write)
HS3ON:HS1ON--High-Side H3:HS1 Enable Bit
Table 8 shows the SPI Control register bits by name.
Table 8. Control Bits Function (Write Operation)
D7 D6 D5 D4 D3 D2 D1 D0
LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1
This bit enables the HSx. Reset clears the HSx bit. * 1 = HSx switched on (refer to Note below). * 0 = HSx switched off. Note If no PWM on HS1 and HS2 is required, the PWMIN terminal must be connected to the VDD terminal.
MODE2:1--Mode Section Bits
LINSL2:1--LIN Baud Rate and Low-Power Mode Selection Bits
The MODE2:1 bits control the operating modes and the watchdog in accordance with Table 10.
Table 10. Mode Selection Bits
MODE2 0 0 1 1 MODE1 0 1 0 1 Description Sleep Mode (32) Stop Mode (32) Watchdog Clear (33) Run (Normal) Mode
These bits select the LIN slew rate and requested lowpower mode in accordance with Table 9. Reset clears the LINSL2:1 bits.
Table 9. LIN Baud Rate and Low-Power Mode Selection Bits
LINSL2 0 0 1 1 LINSL1 0 1 0 1 Description Baud Rate up to 20 kbps (normal) Baud Rate up to 10 kbps (slow) Fast Program Download Baud Rate up to 100 kbps Low-Power Mode (Sleep or Stop) Request
LIN-PU--LIN Pullup Enable Bit
Notes 32. To enter Sleep and Stop mode, a special sequence of SPI commands is implemented. 33. The device stays in Run (Normal) mode.
This bit controls the LIN pullup resistor during Sleep and Stop modes. * 1 = Pullup disconnected in Sleep and Stop modes. * 0 = Pullup connected in Sleep and Stop modes.
To safely enter Sleep or Stop mode and to ensure that these modes are not affected by noise issue during SPI transmission, the Sleep/Stop commands require two SPI transmissions.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Functional Description Functional Device Operation
Sleep Mode Sequence
LINWU/LINFAIL--LIN Status Flag Bit
The Sleep command, as shown in Table 11, has to be sent twice.
Table 11. Sleep Command Bits
LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE 2 MODE 1
This bit indicates a LIN wake-up condition. * 1 = LIN bus wake-up occurred or LIN overcurrent/ overtemperature occurred. * 0 = No LIN bus wake-up occurred.
HVF --High-Voltage Flag Bit
1
1
x
x
x
x
0
0
x = Don't care.
This flag is set on an overvoltage (VSUP1) condition. * 1 = High-voltage condition has occurred. * 0 = no High-voltage condition.
LVF/BATFAIL--Low-Voltage Flag Bit
Stop Mode Sequence The Stop command, as shown in Table 12, has to be sent twice. Table 12. Stop Command Bits
LINSL2 LINSL1 LIN-PU HS3O N HS2O N HS1O N MODE2 MODE1
This flag is set on an undervoltage (VSUP1) condition. * 1 = Low-voltage condition has occurred. * 0 = No low-voltage condition.
VDDT--Voltage Regulator Status Flag Bit
1
1
x
x
x
x
0
1
x = Don't care.
SPI Status Register (Read)
This flag is set as pre-warning in case of an overtemperature condition on the voltage regulator. * 1 = Voltage regulator overtemperature condition, prewarning. * 0 = No overtemperature detected.
HSST--High-Side Status Flag Bit
Table 13 shows the SPI Status register bits by name.
Table 13. Control Bits Function (Read Operation)
D7
INTSRC
D6
LINWU or LINFAIL
D5
HVF
D4
LVF or BATFAIL
D3
VDDT
D2
HSST
D1
L2
D0
L1
This flag is set on overtemperature conditions on one of the high-side outputs. * 1 = HSx off due to overtemperature. * 0 = No overtemperature.
L2:L1-- Wake-Up Inputs L1, L2 Status Flag Bit
INTSCR --Register Content Flags or Interrupt Source
This bit indicates if the register contents reflect the flags or an interrupt/wake-up interrupt source. * 1 = D6:D0 reflects the interrupt or wake-up source. * 0 = No interrupt occurred. Other SPI bits report real time status.
These flags reflect the status of the L2 and L1 input terminals and indicate the wake-up source. * 1 = L2:L1 input high or wake-up by L2:L1 (first register read after wake-up indicated with INTSRC = 1). * 0 = L2:L1 input low.
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Package Dimensions
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below.
10.3 7.6 7.4 5 C 9 B 2.65 2.35
52X
1
54
0.65
PIN 1 INDEX
4 9 B B
18.0 17.8
C L
27
28
5.15
2X 27 TIPS
A
54X
SEATING PLANE
0.3
ABC
0.10 A
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
(0.29) A 0.30 0.25 6 A 0.13 0.38 0.22
M
BASE METAL
R0.08 MIN (0.25) 0.25
GAUGE PLANE PLATING
0 MIN 0.29 0.13
A BC
8
ROTATED 90 CLOCKWISE
SECTION A-A
8 0
0.9 0.5 SECTION B-B
DWB SUFFIX 54-TERMINAL 1365-01 BODY CASE SOIC WIDE PLASTIC PACKAGE ISSUE O 98ASA99294D ISSUE O
DATE 09/19/01
908E624
28
Analog Integrated Circuit Device Data Freescale Semiconductor
Freescale Semiconductor Technical Data
MM908E624DWTAD Rev 2.0, 12/2004
Integrated Triple High-Side Switch with Embedded MCU and LIN Serial Communication for Relay Drivers
Introduction
908E624DW
54-TERMINAL SOICW
This package is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2
=
RJA11 RJA12 RJA21 RJA22
.
P1 P2
DW SUFFIX 98ASA99294D 54-TERMINAL SOICW
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below.
Standards Table 1. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip (C/W) Thermal Resistance RJAmn RJBmn RJAmn RJCmn m = 1, n=1 40 25 57 21 m = 1, n = 2 m = 2, n = 1 31 16 47 12 m = 2, n=2 36 21 52 16
Note For package dimensions, refer to the 908E624 device datasheet.
(c) Freescale Semiconductor, Inc., 2004. All rights reserved.
A
PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0 PTD1/TACH1 NC NC NC PWMIN RST_A IRQ_A NC NC NC L1 L2 HS3 HS2 HS1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD NC RXD WDCONF +E -E OUT VCC AGND VDD NC VSUP1 GND LIN VSUP2
908E624 Terminal Connections
54-Terminal SOICW 0.65 mm Pitch 17.9 mm x 7.5 mm Body
Figure 1. Thermal Test Board Device on Thermal Test Board
Material:
Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air
Table 2.
Thermal Resistance Performance
1 = Power Chip, 2 = Logic Chip (C/W) Area A (mm2) 0 300 600
Terminal Resistance RJAmn
Outline:
m = 1, n=1 58 56 54
m = 1, n = 2 m = 2, n = 1 48 46 45
m = 2, n=2 53 51 50
Area A: Ambient Conditions:
RJAmn is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed.
908E624DW
32
Analog Integrated Circuit Device Data Freescale Semiconductor
70 60
Thermal Resistance (CW)
50 40 30 20 10 0
x
RJA11 RJA22 RJA12 = RJA21
0
300 600 Heat Spreading Area A (mm2)
Figure 2. Device on Thermal Test Board RJA
100
10
Thermal Resistance (CW)
x
RJA11 RJA22 RJA12 = RJA21
1
0.1 1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
time[s]
Time (s)
Figure 3. Transient Thermal Resistance (1.0 W Step Response) Device on Thermal Test Board Area A = 600 (mm2)
908E624DW
Analog Integrated Circuit Device Data Freescale Semiconductor
33
How to Reach Us:
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MM908E624 Rev. 4.0 12/2004

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